The present invention relates to a deficient pixel detecting method and an image processing apparatus, and more particularly, to a method for detecting a deficient pixel signal included in an image signal and an image processing apparatus for correcting a deficient pixel using the detection method.
In a solid-state image sensor, such as a CCD image sensor, a deficiency may occur in a pixel such that the pixel stores a constant amount of charge regardless of the level of the received light and outputs an image signal having a fixed level. To prevent the deficient pixel from affecting the reproduced image, the image signals obtained from the solid-state imaging device undergo a deficiency correction process.
FIG. 1 is a schematic block diagram of an imaging apparatus that performs a pixel deficiency correction process. The imaging apparatus 100 includes a CCD image sensor 1, a driver 2, a timing control circuit 3, a signal processor 4, a deficiency correction circuit 5, and a correction information memory 6.
The image sensor 1 includes a plurality of light receiving pixels (not shown) that are arranged in a matrix. A charge corresponding to the received light of a subject image is stored in each pixel. In accordance with a vertical drive signal xcfx86V and a horizontal drive signal xcfx86H, the image sensor 1 sequentially transfers the charges stored in the light receiving pixels in single line units and generates an image signal Y0 having a predetermined format.
The driver 2 generates the vertical drive signal xcfx86V in accordance with a vertical synchronizing signal VD and generates the horizontal drive signal xcfx86H in accordance with a horizontal synchronizing signal HD. Further, the driver 2 provides the signals xcfx86V, xcfx86H to the image sensor 1 to drive the image sensor 1.
The timing control circuit 3 divides a reference clock, which has a predetermined frequency, generates the vertical synchronizing signal VD, which determines a vertical scan timing, and the horizontal synchronizing signal HD, which determines a horizontal scan timing, and provides the synchronizing signals VD, HD to the driver 2. For example, when the NTSC format is used, a reference clock having a frequency of 14.32 MHz is divided by 910 to generate the horizontal synchronizing signal HD, and the signal HD is divided by 525/2 to generate the vertical synchronous signal VD. Further, the timing control circuit 3 provides the signal processor 4 and the deficiency correction circuit 5 with timing signals that are synchronized with the operation timing of the image sensor 1.
The signal processor 4 performs a sample and hold process and a level correction process on the image signal Y0 provided from the image sensor 1 to generate an image signal Y1. The image signal Y0 alternates between a signal level and a reset level. Thus, for example, during the sample and hold process, the signal processor 4 clamps the reset level and extracts the signal level to generate the image signal Y1 having the signal level from the image signal Y0. Further, during the level correction process, the signal processor 4 performs gain feedback control on the image signal Y0 so that the average level of the image signal Y1 is within a target range. The signal processor 4 sample and holds the image signal Y0 and performs digital processing by A/D converting the sample hold value.
The deficiency correction circuit 5 performs a deficiency correction process on the image signal Y1 in accordance with correction information stored in the correction information memory 6. For example, the information of a deficient pixel is replaced by an average value taken from the preceding and following pixels.
The position of the deficient pixel in the image sensor 1 is stored in the correction information memory 6. For example, the output of the image sensor 1 is monitored to detect the position of the deficient pixel, and the detection result is stored as correction address information in the memory 6.
When a plurality of the CCD image sensors 1 are manufactured from the same semiconductor substrate, the location of a deficient pixel may differ between image sensors 1. Thus, the position of deficient pixels must be detected for each image sensor 1 to generate the correction address information. This increases the cost of the assembly process.
As time passes by, the number of deficient pixels in the image sensor 1 may increase. When such change occurs, the correction address information of the correction information memory 6 must be rewritten. However, a user of the imaging apparatus 100 normally does not have the means to rewrite the correction address information.
It is an object of the present invention to provide a deficient pixel detection method and an image signal processor that adapts to changes of the deficient pixels that occur as time passes by.
To achieve the above object, the present invention provides a method for detecting a deficient pixel from a plurality of pixels. The method includes the steps of computing an average level of signals generated by peripheral pixels that are adjacent to a target pixel, detecting a maximum level and a minimum level of the signals of the peripheral pixels, computing a difference value between the maximum level and the minimum level, generating a first reference value by adding the difference value to the average level and a second reference value by subtracting the difference value from the average level, and determining that the target pixel is deficient when a level of a signal of the target pixel is at least one of greater than the first reference value and less than the second reference value.
A further aspect of the present invention provides an image signal processor for processing a plurality of pixel signals. The image signal processor includes a memory circuit for storing a target pixel signal and peripheral signals corresponding to peripheral pixels that are adjacent to the target pixel and a deficiency detection circuit connected to the memory circuit to compare the level of the target pixel signal with the levels of the peripheral pixel signals to detect whether the target pixel is deficient. The deficiency detection circuit adds a difference value between a maximum level and a minimum level of the peripheral pixel signals to an average level of the peripheral pixel signals to generate a first reference value and subtracts the difference value from the average level to generate a second reference value. The deficiency detection circuit compares the first and second reference values with the level of the target pixel signal to determine the deficiency of the target pixel. A deficiency correction circuit is connected to the deficiency detection circuit to correct the signal of the deficient target pixel.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.